多晶硅锭中硬质点分析及控制研究

以多晶硅锭中硬质点为研究对象,通过实验研究和数值模拟的方法,对多晶硅锭中硬质点进行形貌和成分分析,并提出改善控制方法。研究结果表明硅锭中部的硬质点较细小,主要由SiC组成;硅锭头部的硬质点较粗大,主要由SiC和Si3N4组成,还有少量O的存在。进一步研究发现多晶硅定向凝固铸锭炉的热场结构对于多晶硅锭硬质点形成有直接影响,通过改进热场结构,优化晶体生长界面,显著减少了铸锭中硬质点的数量。     

ZnO基薄膜晶体管的研究

ZnO是一种宽带隙的光电半导体材料,能应用于很多领域,如可用在压敏变阻器、声表面波器件、气敏元件、紫外光探测等。ZnO也可以作为有源层应用于薄膜晶体管(TFT)中。ZnO基薄膜晶体管具有以下突出优势:对于可见光部分平均具有80%以上的透射率,迁移率可以高达36cm2/V·s,开/关电流比大于106,可在较低温度(甚至室温)下制备。基于这些优点,ZnOTFT具有取代有源矩阵液晶显示器中常规a-SiTFT的趋势。同时对ZnOTFT的研究也推动了透明电子学的发展。本文阐述了ZnOTFT优越的电学性能,指出了其目前尚存在的不足,并对其发展前景进行了展望。     

Effects of hot-carrier stress on high performance polycrystalline silicon thin film transistor with a single perpendicular grain boundary

This paper is a report on the effect of a single perpendicular grain boundary on the hot-carrier and high current stability in high performance polycrystalline silicon (poly-Si) thin film transistors (TFTs). Under a hot carrier stress condition (Vg = Vth + 1 V, Vd = 12 V), the poly-Si TFT with a single grain boundary is superior to the poly-Si without any grain boundary because of the smaller free carriers available for electric conduction. The shift of transconductance in poly-Si TFT with a single grain boundary is less than 5% after hot carrier stress during a period of 1000 s. The shift of transconductance is about 25% in the case of the poly-Si TFTs without a grain boundary in the channel. On high current stress, the poly-Si TFT without the grain boundary is less degraded than the poly-Si TFT with the grain boundary because the concentrated electric field near the drain junction is lower.     

非晶硅基薄膜的等离子体刻蚀光发射谱检测

本文研究了采用锁定放大相干检测技术的等离子体光发射谱检测系统。用该系统检测了仅用CF4作为刻蚀气体刻蚀非晶硅基薄膜的等离子体光发射谱。分析了检测结果和刻蚀机理。     

Formation of low-resistivity poly-Si and SiNx films by Cat-CVD for ULSI application

In this paper, bulk-Si metal–oxide–semiconductor field effect transistors (MOSFETs) are fabricated using the catalytic chemical vapor deposition (Cat-CVD) method as an alternative technology to the conventional high-temperature thermal chemical vapor deposition. Particularly, formation of low-resistivity phosphorus (P)-doped poly-Si films is attempted by using Cat-CVD-deposited amorphous silicon (a-Si) films and successive rapid thermal annealing (RTA) of them. Even after RTA processes, neither peeling nor bubbling are observed, since hydrogen contents in Cat-CVD a-Si films can be as low as 1.1%. Both the crystallization and low resistivity of 0.004 Ω·cm are realized by RTA at 1000 °C for only 5 s. It is also revealed that Cat-CVD SiN_x films prepared at 250 °C show excellent oxidation resistance, when the thickness of films is larger than approximately 10 nm for wet O₂ oxidation at 1100 °C. It is found that the thickness required to stop oxygen penetration is equivalent to that for thermal CVD SiN_x prepared at 750 °C. Finally, complementary MOSFETs (CMOSs) of single-crystalline Si were fabricated by using Cat-CVD poly-Si for gate electrodes and SiN_x films for masks of local oxidation of silicon (LOCOS). At 3.3 V operation, less than 1.0 pA μm⁻¹ of OFF leakage current and ON/OFF ratio of 10⁷–10⁸ are realized, i.e. the devices can operate similarly to conventional thermal CVD process.     

Modelling velocity saturation and kink effects in p-channel polysilicon thin-film transistors

Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.     

a—Si：H TFT电流—电压特性研究

本文发展了一种研究ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的新方法。基于局域态电荷密度解析统一模型，提出并深入分析了沟道区有效温度参数的概念，并由此推导出了ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的解析表达式。其理论值与实验值符合很好。该模型可用于ａ－Ｓｉ：Ｈ ＴＦＴ静态特性分析及其电路优化。     

TFT LCD的过压驱动技术探讨

过压驱动技术是提高液晶显示器响应速度的关键技术之一。文章分析了TN型TFT液晶显示的原理及影响响应时间的因素,探讨了过压驱动的原理和系统结构,对灰阶亮度上升和下降两种状态下的应用进行了说明。对液晶显示系统进行了实验分析以及响应时间的测量,结果表明通过过压驱动可以在很大程度上提高液晶显示器的响应时间,有效改善显示画面的动态模糊问题。在0℃的环境温度下,最大灰阶响应时间不超过80ms。     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.